1. Field of the Invention
Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits including transistor elements that comprise a high-k metal gate electrode structure formed in an early process stage.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a great number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Currently, a plurality of process technologies are practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a planar transistor architecture, the distance between the source and drain regions, which is also referred to as channel length.
Presently, the vast majority of integrated circuits are formed on the basis of silicon due to its substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the past 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different silicon regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide has been preferably used as a base material for gate insulation layers that separate the gate electrode, frequently comprised of polysilicon, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by, among other things, the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length for a planar transistor configuration requires an increased capacitive coupling, in combination with sophisticated lateral and vertical dopant profiles in the drain and source regions, to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled planar transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current due to the required enhanced capacitive coupling of the gate electrode to the channel region. That is, conventionally, the thickness of the silicon dioxide layer has been correspondingly reduced to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although usage of high speed transistor elements having an extremely short channel may typically be restricted to high speed applications, whereas transistor elements with a longer channel may be used for less critical applications, such as storage transistor elements, the relatively high leakage current caused by the direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may no longer be compatible with requirements for many types of circuits.
For this reason, new strategies have been developed in overcoming the limitations imposed by high leakage currents of extremely thin silicon oxide-based gate insulation layers. One very promising approach is the replacement of the conventional dielectric materials, at least partially, by dielectric materials having a dielectric constant that is significantly greater than the dielectric constant of silicon dioxide-based materials. For example, dielectric materials, also referred to as high-k dielectric materials, with a dielectric constant of 10.0 and significantly higher may be used, for instance in the form of hafnium oxide, zirconium oxide and the like. In addition to providing a high-k dielectric material in the gate insulation layers, appropriate metal-containing materials may also have to be incorporated since the required work function values for P-channel transistors and N-channel transistors may not be obtained on the basis of standard polysilicon gate materials in combination with the high-k dielectric material. To this end, appropriate metal-containing materials may be provided so as to cover the sensitive high-k dielectric materials and act as a source for incorporating an appropriate metal species, such as lanthanum, aluminum and the like, in order to appropriately adjust the work function for N-channel transistors and P-channel transistors, respectively. Furthermore, due to the presence of a metal-containing conductive material, the generation of a depletion zone, as may typically occur in polysilicon-based electrode materials, may be substantially avoided.
The process of fabricating a sophisticated gate electrode structure on the basis of a high-k dielectric material may require a moderately complex process sequence in order to adjust an appropriate work function for the transistors of different conductivity type and due to the fact that high-k dielectric materials may typically be very sensitive when exposed to certain process conditions, such as high temperatures in the presence of oxygen and the like. Therefore, different approaches have been developed, such as providing the high-k dielectric material at an early manufacturing stage and processing the semiconductor devices with a high degree of compatibility with standard process techniques, wherein the typical electrode material polysilicon may be replaced in a very advanced manufacturing stage with appropriate metals for adjusting the work function of the different transistors and for providing a highly conductive electrode metal. While this approach may provide superior uniformity of the work function and thus of the threshold voltage of the transistors, since the actual adjustment of the work function may be accomplished after any high temperature processes, a complex process sequence for providing the different work function metals in combination with the electrode metal may be required.
In other very promising approaches, the sophisticated gate electrode structures may be formed in an early manufacturing stage, while the further processing may be based on many well-established process strategies. In this case, the high-k dielectric material and any metal species for adjusting the work function may be provided prior to or upon patterning the gate electrode stack, which may comprise well-established materials, such as silicon and silicon/germanium, thereby enabling the further processing on the basis of well-established process techniques. On the other hand, the gate electrode stack and in particular the sensitive high-k dielectric materials, in combination with any metal-containing cap layers, have to remain reliably confined by appropriate materials throughout the entire processing of the semiconductor device.
The encapsulation of the sensitive gate material is accomplished on the basis of silicon nitride materials, i.e., a dielectric cap layer in the gate electrode structure and a silicon nitride spacer structure, wherein the removal of the silicon nitride cap material, which is not only required for maintaining integrity of the silicon material during sophisticated epitaxial growth processes for incorporating a strain-inducing silicon/germanium alloy in P-channel transistors, but is also necessary for performing the complex gate patterning process, may result in significant non-uniformities, as will be explained in more detail with reference to FIGS. 1a-1f. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 that comprises a substrate 101, such as a silicon substrate, in combination with a semiconductor layer 102, such as a silicon layer or a semiconductor material comprising a significant amount of silicon. As illustrated, the semiconductor device 100 further comprises transistors 150A, 150B in an early manufacturing stage, which may be formed in and above active regions 102A, 102B, respectively. An active region is to be understood as a semiconductor region in the layer 102 in which PN junctions for one or more transistors are to be formed. The active regions 102A, 102B are typically laterally delineated by any appropriate isolation structure, such as a shallow trench isolation (not shown). Furthermore, gate electrode structures 160A, 160B are formed on the active regions 102A, 102B, respectively. As previously discussed, the gate electrode structures 160A, 160B comprise a gate insulation layer 161 formed on the active regions 102A and 102B and comprise a high-k dielectric material, such as hafnium oxide-based materials and the like. The gate insulation layers 161 may additionally comprise a conventional dielectric material, such as a silicon oxide-based material, however, with a significantly reduced thickness of approximately 0.8 nm and less. Consequently, the gate insulation layers 161 may represent any appropriate material composition or a stack of layers to provide the desired thickness, for instance, 1.5 nm and more, while, however, the overall dielectric constant may correspond to that of a silicon oxide-based material having a thickness of 1 nm and significantly less so that any leakage currents may be significantly less compared to conventional extremely thin silicon oxide-based materials.
As discussed above, a metal-containing material is formed on the gate insulation layers 161 and has an appropriate composition for the transistor under consideration. For example, a conductive cap layer 162A is provided in the gate electrode structure 160A and may have incorporated therein an appropriate metal species or may represent an appropriate metal species so as to obtain the desired work function. In other cases, an appropriate work function metal species may also be incorporated in the gate dielectric material 161, depending on the overall process strategy. Similarly, a metal-containing material layer 162B is formed so as to result in a desired work function for the gate electrode structure 160B. In the example shown, the transistor 150A represents a P-channel transistor, while the transistor 150B is an N-channel transistor. In this case, for instance, aluminum may be used as a work function metal species for the gate electrode structure 160A, while lanthanum may be used as a work function metal species for the gate electrode structure 160B. It should be appreciated that, in other approaches, the metal-containing cap layers 162A, 162B may have substantially the same configuration, while the work function adjusting species may be incorporated in the gate dielectric material 161, thereby obtaining the desired work functions for the transistors 150A, 150B, respectively.
The gate electrode structures 160A, 160B further comprise an additional electrode material 163, such as silicon, silicon/germanium and the like, which is formed above the conductive cap layers 162A, 162B, which represent a part of the electrode material of the gate electrode structures. Furthermore, a silicon nitride cap layer 164 is formed above the additional electrode material 163. As indicated above, the silicon nitride cap material 164 is used for patterning the gate electrode structures 160A, 160B and may also act as a mask material in sophisticated applications, in which a strain-inducing semiconductor alloy 151, such as a silicon/germanium, is to be formed in the active region of one or both of the transistors 150A, 150B. In the example shown, the strain-inducing semiconductor material 151 is selectively provided in the active region 102A in the form of a compressive strain-inducing material in order to enhance performance of the P-channel transistor 150A. It is well known that, for a standard crystallographic configuration of the active region 102A, a compressive strain component along the current flow direction, i.e., in FIG. 1a, the horizontal direction within a channel region 152 of a P-channel transistor, may result in superior charge carrier mobility and, thus, current drive capability.
Moreover, as discussed above, a silicon nitride-based sidewall spacer structure 155, which may comprise a liner material 155A in combination with a spacer element 155B, is provided to protect the sidewalls of the electrode material 163 and, in particular, of the sensitive materials 162A, 162B and 161. The liner 155A and the spacer element 155B may typically be comprised of a dense silicon nitride material so as to provide a desired high chemical resistivity. On the other hand, the materials of the spacer structure 155 may be provided in the form of non-patterned layers for the transistor 150B in order to provide a growth mask for forming the strain-inducing semiconductor material 151 in the active region 102A substantially without affecting the transistor 150B.
The semiconductor device 100 as illustrated in FIG. 1a is typically formed on the basis of the following process strategies. After forming any isolation structures and, thus, laterally delineating the active regions 102A, 102B, appropriate materials for the gate insulation layers 161 and one of the layers 162A and 162B are formed by any appropriate deposition technique. Thereafter, the conductive cap material is appropriately patterned and the other one of the layers 162A, 162B is deposited, possibly followed by any heat treatments in order to appropriately diffuse a work function adjusting species towards the gate insulation layers 161. Depending on the process strategy, corresponding work function metal species, such as aluminum, lanthanum and the like, may be provided as individual material layers, followed or sandwiched by any other appropriate material, such as titanium nitride, wherein some or all of these material layers may be removed after having diffused the work function metal species into the gate dielectric materials 161. Thereafter, a further conductive cap material, such as titanium nitride, may commonly be formed in the gate electrode structures 160A, 160B. In other strategies, an appropriate stack of conductive materials may be individually provided in the gate electrode structures 160A, 160B so as to achieve the required electronic characteristics.
It should be appreciated that adaptation of the threshold voltage may require a corresponding adjustment or shift of the band gap of the semiconductor material in the channel region 152, which may, for instance, be accomplished by incorporating an appropriate material, such as a silicon/germanium material, in the channel region 152 of P-channel transistors, which has a reduced band gap compared to a pure silicon material. To this end, a silicon/germanium material (not shown) may be formed in the active region 102A prior to forming the gate electrode structures 160A, 160B. Consequently, the corresponding silicon/germanium material is then to be considered as a portion of the channel region 152. After providing the appropriate work function metal species or after performing corresponding diffusion processes, the electrode material 163, for instance in the form of amorphous silicon, is deposited, followed by the deposition of the silicon nitride cap layer 164, wherein additional materials, such as hard mask materials in the form of amorphous carbon and the like, may also be provided as required. Thereafter, a sophisticated lithography process and an anisotropic etch sequence are performed, in which the silicon nitride cap layer 164 is used for achieving the critical dimensions of 50 nm and significantly less in accordance with the overall design rules. Next, the materials 155A, 155B are formed, for instance by thermally activated chemical vapor deposition (CVD) techniques, such as multilayer deposition techniques and the like, possibly in combination with plasma enhanced CVD techniques, low pressure CVD and the like, in order to form, in particular, the liner material 155A as a very dense silicon nitride material that reliably confines the sidewalls of the gate electrode structures. Thereafter, an etch mask is provided to cover the transistor 150B in order to form the spacer element 155B and possibly etch into the active region 102A in order to form cavities therein. Next, a selective epitaxial growth process is performed in which the strain-inducing semiconductor material 151 is grown in the previously formed cavities, while the silicon nitride cap layer 164, the spacer structure 155 and the non-patterned material 155 above the transistor 150B may act as a growth mask so as to avoid undue material deposition thereon.
FIG. 1b schematically illustrates the semiconductor device 100 in a manufacturing stage in which an etch mask 103 covers the active region 102A and exposes the gate electrode structure 160B and the active region 102B. An etch process 104 is applied in order to form the spacer structure 155 on sidewalls of the gate electrode structure 160B, which is accomplished by well-established plasma assisted etch recipes. It should be appreciated that, during the etch process 104, a certain amount of material erosion in the active region 102B, or at least a material modification, may occur. For example, plasma assisted etch recipes for removing silicon nitride material may exhibit a self limiting behavior when interacting with the underlying silicon material, wherein silicon dioxide is generated, which may then act as an efficient etch stop material, since the corresponding etch chemistry is highly selective to silicon dioxide material. After the etch process 104, the etch mask 103 is removed and consequently the gate electrode structures 160A, 160B have the sidewall spacer structures 155 provided on both gate electrode structures. During the further processing, the dielectric cap layers 164 have to be removed, which, however, may have a significant influence on the resulting surface topography and, thus, on the resulting transistor characteristics. For instance, upon removing the dielectric cap material 164, wet chemical etch recipes on the basis of phosphoric acid are typically applied, which, thus, could cause a significant degree of material erosion in the spacer structure 155. For this reason, the spacer structure 155 is typically protected by providing a sacrificial spacer element having an increased etch resistivity with respect to the silicon nitride etch chemistry, which may be accomplished on the basis of an oxide spacer.
FIG. 1c schematically illustrates the semiconductor device 100 with an oxide spacer layer 166, which is etched during an etch process 105 in order to form sacrificial oxide spacers 166S on the sidewall spacer structure 155. Consequently, during the etch process 105, a certain degree of recessing may occur, in particular in the active region 102B, due to any previously performed etch processes and oxide materials created, for instance, during the silicon nitride etch process, as discussed above.
FIG. 1d schematically illustrates the device 100 when exposed to a further etch process 106 for removing the dielectric cap material 164 on the basis of, for instance, phosphoric acid, thereby also causing a certain degree of recessing in the active regions 102A, 102B, as indicated by 102R.
FIG. 1e schematically illustrates the semiconductor device 100 in a manufacturing stage in which the sacrificial spacer elements 166S (FIG. 1d) are removed, which may be accomplished on the basis of diluted hydrofluoric acid (HF). It should be appreciated that this etch process and also the preceding etch process for forming the sacrificial spacer elements 166S (FIG. 1d) may also result in a significant material erosion in any isolation structures (not shown), thereby contributing to a pronounced surface topography during the further processing, which may also negatively affect overall device characteristics.
FIG. 1f schematically illustrates the device 100 during an implantation sequence 107 in order to form drain and source extension regions 153E in the active region 102A. To this end, an implantation mask 108 is provided that covers the active region 102B. In the example shown, drain extension regions 153E have already been formed in the active region 102B, possibly in combination with counter-doped regions or halo regions 153H, which are typically required in sophisticated transistors in order to appropriately adjust the transistor off-current or the like. During the implantation sequence 107, the recesses 102R may affect the resulting configuration of the extension regions 153E and of the halo regions, which are to be formed on the basis of a tilted implantation process. Generally, the implantation of the halo regions 153H may require a lower implantation energy as would be desirable due to the presence of the recess 102R and due to the reduced ion blocking effect of the gate electrode structures 160A, 160B in order to avoid undue deposition of dopant species in the channel regions 152, which may otherwise occur when a desired higher implantation energy would be selected for obtaining an increased penetration depth of the halo regions 153H. On the other hand, forming the extension regions 153E and the halo regions 153H prior to removing the dielectric cap material 164 (FIG. 1d) may be a less attractive approach, since, in this case, a significant amount of the dopants in the extension regions 153E would be removed in the subsequent process sequence for removing the dielectric cap layer 164 due to the material erosion in close proximity to the channel region 152. In this case, additional implantation processes would be required so as to appropriately connect deep drain and source regions still to be formed with the drain and source extension regions. Consequently, it is very difficult to provide appropriate dopant profiles in the active regions 102A, 102B without introducing significant additional process complexity, for instance by performing additional implantation processes and associated lithography steps. Consequently, although the approach of providing sophisticated high-k metal gate electrode structures with appropriately set work function values at an early manufacturing stage is basically a promising approach, the inferior dopant profiles or the significantly increased complexity of the overall process flow may make this concept less attractive.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.